Achieving Optimal Performance During Physical Verification

Key steps to take to ensure you are achieving the best throughput for your IC design

With increased complexity in design layout requirements at each new node, the compute burden placed on physical verification has grown exponentially. At the same time, designers are generally faced with less time to get their designs out the door. In this white paper we will cover: Benefits of using the latest foundry rule decks; Advantages of moving to the most recent Calibre releases; Best practices for leveraging multiple compute resources to scale PV runtimes.

w menb25 - Achieving Optimal Performance During Physical Verification

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